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19-2315; Rev 0; 1/02 Dual, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC General Description The MAX5822 is a dual, 12-bit, voltage-output, digital-toanalog converter (DAC) with an I2CTM-compatible, 2-wire interface that operates at clock rates up to 400kHz. The device operates from a single 2.7V to 5.5V supply and draws only 115A at VDD = 3.6V. A power-down mode decreases current consumption to less than 1A. The MAX5822 features three software-selectable powerdown output impedances: 100k, 1k, and high impedance. Other features include internal precision Rail-to-Rail(R) output buffers and a power-on reset (POR) circuit that powers up the DAC in the 100k power-down mode. The MAX5822 features a double-buffered I2C-compatible serial interface that allows multiple devices to share a single bus. All logic inputs are CMOS-logic compatible and buffered with Schmitt triggers, allowing direct interfacing to optocoupled and transformer-isolated interfaces. The MAX5822 minimizes digital noise feedthrough by disconnecting the clock (SCL) signal from the rest of the device when an address mismatch is detected. The MAX5822 is specified over the extended temperature range of -40C to +85C and is available in a miniature 8-pin MAX package. Refer to the MAX5821 data sheet for the 10-bit version. o Ultra-Low Supply Current 115A at VDD = 3.6V 135A at VDD = 5.5V o 300nA Low-Power Power-Down Mode o Single 2.7V to 5.5V Supply Voltage o Fast 400kHz I2C-Compatible 2-Wire Serial Interface o Schmitt-Trigger Inputs for Direct Interfacing to Optocouplers o Rail-to-Rail Output Buffer Amplifiers o Three Software-Selectable Power-Down Output Impedances 100k, 1k, and High Impedance o Read-Back Mode for Bus and Data Checking o Power-On Reset to Zero o 8-Pin MAX Package Features MAX5822 Ordering Information PART MAX5822LEUA MAX5822MEUA TEMP RANGE -40oC to +85oC -40 C to +85 C o o Applications Digital Gain and Offset Adjustments Programmable Voltage and Current Sources Programmable Attenuation VCO/Varactor Diode Control Low-Cost Instrumentation Battery-Powered Instrumentation PINPACKAGE 8 MAX 8 MAX ADDRESS 0111 00X 1011 00X Typical Operating Circuit VDD C SDA VDD SCL RP RP Pin Configuration TOP VIEW VDD 1 GND 2 8 7 OUTB OUTA REF SDA RS RS SCL RS SDA MAX5822 REF VDD OUTA OUTB MAX5822 ADD 3 6 5 SCL 4 SCL RS SDA REF MAX5822 VDD OUTA OUTB MAX Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. I2C is a trademark of Philips Corp. REF ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. Dual, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5822 ABSOLUTE MAXIMUM RATINGS VDD, SCL, SDA to GND ............................................-0.3V to +6V OUT_, REF, ADD to GND..............................-0.3V to VDD + 0.3V Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 8-Pin MAX (derate 4.5mW above +70C) ..................362mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Maximum Junction Temperature .....................................+150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25C.) (Note 1) PARAMETER STATIC ACCURACY (NOTE 2) Resolution Integral Nonlinearity Differential Nonlinearity Zero-Code Error Zero-Code Error Tempco Gain Error Gain-Error Tempco Power-Supply Rejection Ratio DC Crosstalk REFERENCE INPUT Reference Input Voltage Range Reference Input Impedance Reference Current DAC OUTPUT Output Voltage Range DC Output Impedance Short-Circuit Current Wake-Up Time DAC Output Leakage Current DIGITAL INPUTS (SCL, SDA) Input High Voltage Input Low Voltage VIH VIL 0.7 VDD 0.3 VDD V V No load (Note 4) Code = 800 hex VDD = 5V, VOUT = full scale (short to GND) VDD = 3V, VOUT = full scale (short to GND) VDD = 5V VDD = 3V Power-down mode = high impedance, VDD = 5.5V, VOUT_ = VDD to GND 0 1.2 42.2 15.1 8 8 0.1 1 VDD V mA s A Power-down mode VREF 0 65 90 0.3 1 VDD V k A PSRR Code = FFF hex, VDD = 4.5V to 5.5V GE Code = FFF hex N INL DNL ZCE (Note 3) Guaranteed monotonic (Note 3) Code = 000 hex, VDD = 2.7V 6 2.3 -0.8 0.26 58.8 30 -3 12 2 16 1 40 Bits LSB LSB mV ppm/oC %FSR ppm/oC dB V SYMBOL CONDITIONS MIN TYP MAX UNITS 2 _______________________________________________________________________________________ Dual, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25C.) (Note 1) PARAMETER Input Hysteresis Input Leakage Current Input Capacitance DIGITAL OUTPUT (SDA) Output Logic Low Voltage Three-State Leakage Current Three-State Output Capacitance DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time Digital Feedthrough Digital-to-Analog Glitch Impulse DAC to DAC Crosstalk POWER SUPPLIES Supply Voltage Range Supply Current with No Load Power-Down Supply Current Serial Clock Frequency Bus Free Time Between STOP and START Conditions START Condition Hold Time SCL Pulse Width Low SCL Pulse Width High Repeated START Setup Time Data Hold Time Data Setup Time SDA and SCL Receiving Rise Time SDA and SCL Receiving Fall Time SDA Transmitting Fall Time VDD IDD IDDPD fSCL tBUF tHD,STA tLOW tHIGH tSU,STA tHD,DAT tSU,DAT tr tf tf (Note 5) (Note 5) (Note 5) All digital inputs at 0 or VDD = 3.6V All digital inputs at 0 or VDD = 5.5V All digital inputs at 0 or VDD = 5.5V 0 1.3 0.6 1.3 0.6 0.6 0 100 0 0 20 + 0.1Cb 300 300 250 0.9 2.7 115 135 0.3 5.5 205 215 1 400 A kHz s s s s s s ns ns ns ns V A SR To 1/2LSB code 400 hex to C00 hex or C00 hex to 400 hex (Note 5) Code = 000 hex, digital inputs from 0 to VDD Major carry transition (code = 7FF hex to 800 hex and 800 hex to 7FF hex) 0.5 4 0.2 12 2.4 12 V/s s nV-s nV-s nV-s VOL IL ISINK = 3mA Digital inputs = 0 or VDD 0.1 6 0.4 1 V A pF Digital inputs = 0 or VDD SYMBOL CONDITIONS MIN 0.05 VDD 0.1 6 1 TYP MAX UNITS V A pF MAX5822 TIMING CHARACTERISTICS (FIGURE 1) _______________________________________________________________________________________ 3 Dual, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5822 ELECTRICAL CHARACTERISTICS (continued) (VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5k, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VDD = +5V, TA = +25C.) (Note 1) PARAMETER STOP Condition Setup Time Bus Capacitance Maximum Duration of Suppressed Pulse Widths SYMBOL tSU,STO Cb tSP (Note 5) 0 CONDITIONS MIN 0.6 400 50 TYP MAX UNITS s pF ns Note 1: Note 2: Note 3: Note 4: Note 5: All devices are 100% production tested at TA = +25C and are guaranteed by design at TA = TMIN to TMAX. Static specifications are tested with the output unloaded. Linearity is guaranteed from codes 115 to 3981. Offset and gain error limit the FSR. Guaranteed by design. Not production tested. Typical Operating Characteristics (VDD = +5V, RL = 5k, TA = +25C.) INTEGRAL NONLINEARITY vs. INPUT CODE MAX5822 toc01 INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE MAX5822 toc02 INTEGRAL NONLINEARITY vs. TEMPERATURE MAX5822 toc03 4 3 2 INL (LSB) 5 5 4 4 0 -1 -2 INL (LSB) INL (LSB) 1 3 3 2 2 1 -3 -4 0 1024 2048 INPUT CODE 3072 4096 0 2.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V) 1 0 -40 -15 10 35 60 85 TEMPERATURE (C) DIFFERENTIAL NONLINEARITY vs. INPUT CODE 0.75 0.50 DNL (LSB) DNL (LSB) 0.25 0 -0.25 -0.50 -0.75 -1.00 0 1024 2048 INPUT CODE 3072 4096 -1.00 2.7 MAX5822 toc04 DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE MAX5822 toc05 DIFFERENTIAL NONLINEARITY vs. TEMPERATURE MAX5822 toc06 1.00 0 0 -0.25 DNL (LSB) 3.4 4.1 4.8 5.5 -0.25 -0.50 -0.50 -0.75 -0.75 -1.00 -40 -15 10 35 60 85 SUPPLY VOLTAGE (V) TEMPERATURE (C) 4 _______________________________________________________________________________________ Dual, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC Typical Operating Characteristics (continued) (VDD = +5V, RL = 5k, TA = +25C.) ZERO-CODE ERROR vs. SUPPLY VOLTAGE MAX5822 toc07 MAX5822 ZERO-CODE ERROR vs. TEMPERATURE MAX5822 toc08 GAIN ERROR vs. SUPPLY VOLTAGE MAX5822 toc09 10 10 -2.0 8 ZERO-CODE ERROR (mV) 8 ZERO-CODE ERROR (mV) -1.6 GAIN ERROR (%FSR) 6 6 -1.2 4 4 -0.8 2 NO LOAD 0 2.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V) 2 NO LOAD 0 -40 -15 10 35 60 85 TEMPERATURE (C) -0.4 NO LOAD 2.7 3.4 4.1 4.8 5.5 0 SUPPLY VOLTAGE (V) GAIN ERROR vs. TEMPERATURE MAX5822 toc10 DAC OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT (NOTE 6) MAX5822 toc11 DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT (NOTE 6) MAX5822 toc12 -2.0 6 5 DAC OUTPUT VOLTAGE (V) 4 3 2 1 2.5 DAC OUTPUT VOLTAGE (V) -1.6 GAIN ERROR (%FSR) 2.0 -1.2 1.5 CODE = 400 hex -0.8 1.0 -0.4 NO LOAD -40 -15 10 35 60 85 0.5 CODE = FFF hex 0 0 2 4 6 8 10 OUTPUT SOURCE CURRENT (mA) 0 0 2 4 6 8 10 OUTPUT SINK CURRENT (mA) 0 TEMPERATURE (C) SUPPLY CURRENT vs. INPUT CODE MAX5822 toc13 SUPPLY CURRENT vs. TEMPERATURE MAX5822 toc14 SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX5822 toc15 180 180 180 SUPPLY CURRENT (A) SUPPLY CURRENT (A) SUPPLY CURRENT (A) 160 160 160 140 140 140 120 120 NO LOAD CODE = FFF hex -40 -15 10 35 60 85 120 CODE = FFF hex NO LOAD 100 2.7 3.4 4.1 4.8 5.5 SUPPLY VOLTAGE (V) 100 0 819 1638 2457 3276 4096 INPUT CODE 100 TEMPERATURE (C) _______________________________________________________________________________________ 5 Dual, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5822 Typical Operating Characteristics (continued) (VDD = +5V, RL = 5k, TA = +25C.) POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE POWER-DOWN SUPPLY CURRENT (nA) ZOUT = HIGH IMPEDANCE NO LOAD 400 MAX5822 toc16 POWER-UP GLITCH MAX5822 toc17 EXITING SHUTDOWN MAX5822 toc18 500 VDD 5V 300 TA = +25C 200 TA = -40C 0 OUT_ 500mV/div OUT_ 100 TA = +85C 10mV/div CLOAD = 200pF CODE = 800 hex 0 2.7 3.4 4.1 4.8 5.5 100s/div 2s/div SUPPLY VOLTAGE (V) MAJOR-CARRY TRANSITION (POSITIVE) MAX5822 toc19 MAJOR-CARRY TRANSITION (NEGATIVE) MAX5822 toc20 SETTLING TIME (POSITIVE) MAX5822 toc21 OUT_ 5mV/div OUT_ 5mV/div OUT_ 500mV/div CLOAD = 200pF RL = 5k CODE = 7FF hex TO 800 hex 2s/div CLOAD = 200pF RL = 5k CODE = 800 hex TO 7FF hex 2s/div CLOAD = 200pF CODE = 400 hex TO C00 hex 2s/div SETTLING TIME (NEGATIVE) MAX5822 toc22 DIGITAL FEEDTHROUGH MAX5822 toc23 CROSSTALK MAX5822 toc24 SCL 2V/div VOUTA 2V/div OUT_ 500mV/div OUT_ CLOAD = 200pF CODE = C00 hex TO 400 hex 2s/div 40s/div CLOAD = 200pF fSCL = 12kHz CODE = 000 hex V 2mV/div OUTB 1mV/div 4s/div Note 6: The ability to drive loads greater than 5k is not implied. 6 _______________________________________________________________________________________ Dual, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC Pin Description PIN 1 2 3 4 5 6 7 8 NAME VDD GND ADD SCL SDA REF OUTA OUTB Power Supply Ground Address Select. A logic high sets the address LSB to 1; a logic low sets the address LSB to 0 Serial Clock Input Bidirectional Serial Data Interface Reference Input DAC A Output DAC B Output FUNCTION MAX5822 Detailed Description The MAX5822 is a dual, 12-bit, voltage-output DAC with an I2C/SMBus-compatible 2-wire interface. The device consists of a serial interface, power-down circuitry, two input and DAC registers, two 12-bit resistor string DACs, two unity-gain output buffers, and output resistor networks. The serial interface decodes the address and control bits, routing the data to the proper input or DAC register. Data can be directly written to the DAC register, immediately updating the device output, or can be written to the input register without changing the DAC output. Both registers retain data as long as the device is powered. with the output buffers disabled and the outputs pulled to GND through the 100k termination resistor. Following power-up, a wake-up command must be initiated before any conversions are performed. Power-Down Modes The MAX5822 has three software-controlled, low-power power-down modes. All three modes disable the output buffers and disconnect the DAC resistor strings from REF, reducing supply current draw to 1A and the reference current draw to less than 1A. In power-down mode 0, the device output is high impedance. In power-down mode 1, the device output is internally pulled to GND by a 1k termination resistor. In powerdown mode 2, the device output is internally pulled to GND by a 100k termination resistor. Table 1 shows the power-down mode command words. Upon wake-up, the DAC output is restored to its previous value. Data is retained in the input and DAC registers during power-down mode. DAC Operation The MAX5822 uses a segmented resistor string DAC architecture, which saves power in the overall system and guarantees output monotonicity. The MAX5822's input coding is straight binary, with the output voltage given by the following equation: VOUT _ = VREF x (D) 2N Digital Interface The MAX5822 features an I2C/SMBus-compatible 2wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). The MAX5822 is SMBus compatible within the range of VDD = 2.7V to 3.6V. SDA and SCL facilitate bidirectional communication between the MAX5822 and the master at rates up to 400kHz. Figure 1 shows the 2-wire interface timing diagram. The MAX5822 is a transmit/receive slave-only device, relying upon a master to generate a clock signal. The master (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer. A master device communicates to the MAX5822 by transmitting the proper address followed by command and/or data words. Each transmit sequence is framed by a START (S) or repeated START (Sr) condition and a STOP (P) condition. Each word transmitted over the 7 where N = 12 (bits), and D = the decimal value of the input code (0 to 4095). Output Buffer The MAX5822 analog outputs are buffered by precision, unity-gain followers that slew 0.5V/s. Each buffer output swings rail-to-rail, and is capable of driving 5k in parallel with 200pF. The output settles to 0.5LSB within 4s. Power-On Reset The MAX5822 features an internal POR circuit that initializes the device upon power-up. The DAC registers are set to zero scale and the device is powered down, _______________________________________________________________________________________ Dual, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC Table 1. Power-Down Command Bits POWER-DOWN COMMAND BITS PD1 0 0 PD0 0 1 Power-up device. DAC output restored to previous value. Power-down mode 0. Power down device with output floating. Power-down mode 1. Power down device with output terminated with 1k to GND. Power-down mode 2. Power down device with output terminated with 100k to GND. MODE/FUNCTION 1 0 1 1 START and STOP Conditions When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-tolow transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high (Figure 2). A START condition from the master signals the beginning of a transmission to the MAX5822. The master terminates transmission by issuing a notacknowledge followed by a STOP condition (see Acknowledge Bit (ACK)). The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active. When a STOP condition or incorrect address is detected, the MAX5822 internally disconnects SCL from the serial interface until the next START condition, minimizing digital noise and feedthrough. Early STOP Conditions The MAX5822 recognizes a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition (Figure 3). This condition is not a legal I2C format; at least one clock pulse must separate any START and STOP conditions. Repeated START Conditions A repeated START (S r ) condition may indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation. S r may also be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX5822 serial interface supports continuous write operations with or without an Sr condition separating them. Continuous read operations require Sr conditions because of the change in direction of data flow. MAX5822 bus is 8 bits long and is always followed by an acknowledge clock pulse. The MAX5822 SDA and SCL drivers are open-drain outputs, requiring a pullup resistor to generate a logic high voltage (see the Typical Operating Circuit). Series resistors RS are optional. These series resistors protect the input stages of the MAX5822 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). Both SDA and SCL idle high when the I2C bus is not busy. SDA tSU, DAT tLOW SCL tHIGH tHD, STA tR tF tHD, DAT tSU, STA tHD, STA tSP tSU, STO tBUF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 1. 2-Wire Serial Interface Timing Diagram 8 _______________________________________________________________________________________ Dual, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC S SCL Sr P SDA Figure 2. START and STOP Conditions waits for a START condition followed by its slave address. The serial interface compares each address value bit by bit, allowing the interface to power down immediately, if an incorrect address is detected. The LSB of the address word is the Read/Write (R/W) bit. R/W indicates whether the master is writing to or reading from the MAX5822 (R/W = 0 selects the write condition, R/W = 1 selects the read condition). After receiving the proper address, the MAX5822 issues an ACK by pulling SDA low for one clock cycle. The MAX5822 has four different factory/user-programmed addresses (Table 2). Address bits A6 through A1 are preset, while A0 is controlled by ADD. Connecting ADD to GND sets A0 = 0. Connecting ADD to V DD sets A0 = 1. This feature allows up to four MAX5822s to share the same bus. MAX5822 SCL SDA STOP START Table 2. MAX5822 I2C Slave Addresses PART LEGAL STOP CONDITION VADD GND VDD GND VDD DEVICE ADDRESS (A6...A0) 0111 000 0111 001 1011 000 1011 001 MAX5822L MAX5822L MAX5822M MAX5822M SCL SDA START ILLEGAL STOP ILLEGAL EARLY STOP CONDITION Figure 3. Early STOP Conditions Acknowledge Bit (ACK) The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data word. ACK is always generated by the receiving device. The MAX5822 generates an ACK when receiving an address or data by pulling SDA low during the ninth clock period. When transmitting data, the MAX5822 waits for the receiving device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by the 7bit slave address (Figure 4). When idle, the MAX5822 Write Data Format In write mode (R/W = 0), data that follows the address byte controls the MAX5822 (Figure 5). Bits C3-C0 configure the MAX5822 (Table 3). Bits D11-D0 are DAC data. Input and DAC registers update on the falling edge of SCL during the acknowledge bit. Should the write cycle be prematurely aborted, data is not updated and the write cycle must be repeated. Figure 6 shows two example write data sequences. Extended Command Mode The MAX5822 features an extended command mode that is accessed by setting C3-C0 = 1 and D11-D8 = 0. The next data byte writes to the shutdown registers S A6 A5 A4 A3 A2 A1 A0 R/W Figure 4. Slave Address Byte Definition C3 C2 C1 C0 D11 D10 D9 D8 Figure 5. Command Byte Definition 9 _______________________________________________________________________________________ Dual, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5822 MSB S A6 A5 A4 A3 A2 A1 A0 LSB R/W ACK MSB C3 C2 C1 C0 D11 D10 D9 LSB D8 ACK MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 ACK P EXAMPLE-WRITE DATA SEQUENCE MSB S A6 A5 A4 A3 A2 A1 A0 LSB R/W ACK MSB C3 C2 C1 C0 D11 D10 D9 LSB D8 ACK MSB X X X X B A PD1 LSB PD0 ACK P EXAMPLE-WRITE TO POWER-DOWN REGISTER SEQUENCE Figure 6. Example Write-Command Sequences (Figure 7). Setting bits A or B to 1 sets that DAC to the selected power-down mode based on the states of PD0 and PD1 (Table 1). Any combination of the DACs can be controlled with a single write sequence. Read Data Format In read mode (R/W = 1), the MAX5822 writes the contents of the DAC register to the bus. The direction of data flow reverses following the address acknowledge by the MAX5822. The device transmits the first byte of data, waits for the master to acknowledge, then transmits the second byte. Figure 8 shows an example-read data sequence. I2C Compatibility The MAX5822 is compatible with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain that pulls the data line low during the ninth clock pulse. The Typical Operating Circuit shows a typical I2C application. The communication protocol supports the standard I 2 C 8-bit communications. The general call address is ignored. The MAX5822 address is compatible with the 7-bit I2C addressing protocol only. No 10-bit address formats are supported. X X X X B A PD1 PD0 Figure 7. Extended Command Byte Format caused by the SCL signal on a static output. The serial interface reconnects the SCL signal once a valid START condition is detected. Applications Information Digital Inputs and Interface Logic The MAX5822 2-wire digital interface is I 2C/SMBus compatible. The two digital inputs (SCL and SDA) load the digital input serially into the DAC. Schmitt-trigger buffered inputs allow slow-transition interfaces, such as optocouplers to interface directly to the device. The digital inputs are compatible with CMOS logic levels. Power-Supply Bypassing and Ground Management Careful PC board layout is important for optimal system performance. Keep analog and digital signals separate to reduce noise injection and digital feedthrough. Use a ground plane to ensure that the ground return from GND to the power-supply ground is short and low impedance. Bypass V DD with a 0.1F capacitor to ground as close to the device as possible. Digital Feedthrough Suppression When the MAX5822 detects an address mismatch, the serial interface disconnects the SCL signal from the core circuitry. This minimizes digital feedthrough 10 ______________________________________________________________________________________ Dual, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC Chip Information TRANSISTOR COUNT: 11,186 PROCESS: BiCMOS MAX5822 Table 3. Command Byte Definitions SERIAL DATA INPUT C3 0 C2 0 C1 0 C0 0 D11 DAC DATA D10 DAC DATA D9 DAC DATA D8 DAC DATA FUNCTION Load DAC A input and DAC registers with new data. Contents of DAC B input registers are transferred to the DAC register. Both outputs are updated. Load DAC B input and DAC registers with new data. Contents of DAC A input registers are transferred to the DAC register. Both outputs are updated simultaneously. Load DAC A input register with new data. DAC outputs remain unchanged. Load DAC B input register with new data. DAC outputs remain unchanged. Data in all input registers is transferred to respective DAC registers. All DAC outputs are updated simultaneously. New data is loaded into DAC A input register. Data in all input registers is transferred to respective DAC registers. All DAC outputs are updated simultaneously. New data is loaded into DAC B input register. Load all DACs with new data and update all DAC outputs simultaneously. Both input and DAC registers are updated with new data. Load all input registers with new data. DAC outputs remain unchanged. Update all DAC outputs simultaneously. Device ignores D11-D8. Do not send the data byte. Extended command mode. The next word writes to the power-down registers (Extended Command Mode). Read DAC A data. The device expects an Sr condition followed by an address word with R/W = 1. Read DAC B data. The device expects an Sr condition followed by an address word with R/W = 1. 0 0 0 1 DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA DAC DATA 0 0 1 1 0 0 0 1 1 0 0 0 1 0 0 1 DAC DATA DAC DATA DAC DATA DAC DATA 1 1 0 0 DAC DATA DAC DATA X 0 0 0 DAC DATA DAC DATA X 0 0 0 DAC DATA DAC DATA X 0 0 1 DAC DATA DAC DATA X 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 ______________________________________________________________________________________ 11 Dual, 12-Bit, Low-Power, 2-Wire, Serial Voltage-Output DAC MAX5822 MSB S A6 A5 A4 A3 A2 A1 A0 LSB R/W =0 ACK MSB C3 C2 C1 C0 D11 D10 D9 LSB D8 ACK DATA BYTES GENERATED BY MASTER DEVICE MSB Sr A6 A5 A4 A3 A2 A1 A0 LSB R/W =1 ACK MSB X X PD1 PD0 D11 D10 D9 LSB D8 ACK DATA BYTES GENERATED BY MAX5822 MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 ACK P ACK GENERATED BY MASTER DEVICE Figure 8. Example Read Word Data Sequence Functional Diagram REF INPUT REGISTER A MUX AND DAC REGISTER 12-BIT DAC A MAX5822 OUTA RESISTOR NETWORK INPUT REGISTER B MUX AND DAC REGISTER 12-BIT DAC B RESISTOR NETWORK OUTB SERIAL INTERFACE POWER-DOWN CIRCUITRY SDA ADD SCL VDD GND 12 ______________________________________________________________________________________ Dual, 12-Bit, Low-Power, 2-Wire Serial Voltage Output DAC Package Information 8LUMAXD.EPS MAX5822 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. |
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